1. Field of the Invention
The present invention relates to a semiconductor integrated circuit. More particularly, the present invention relates to a latch circuit which reduces the number of circuit elements connected to an input or an output to reduce load at the input or output to thereby achieve high-speed operation.
2. Description of the Related Art
A latch circuit has the function of temporarily holding (i.e., storing) signals. FIGS. 1–3 illustrate examples of related art latch circuits. As shown in FIGS. 1–3, to hold signals the related art latch circuits include a loop circuit, which is formed of two stages of inverters to hold signals. A latch circuit may be connected with a plurality of input circuits and output circuits. In such a latch circuit, the number of terminals respectively connected to input circuit and output circuits has increased.
The related art latch circuits shown in FIGS. 1–3 respectively include a plurality of input circuits and output circuits connected thereto.
The example of the related art latch circuit shown in FIG. 1 includes an input node N1, and an output node N2. Two input circuits (not shown) are connected at the input node N1, which is the input of the latch circuit. Specifically, an input I1 from a first input circuit and an input I2 from a second input circuit are connected at the input node N1. Moreover, two output circuits (not shown) are connected by the output node N2, which is the output of the latch circuit. Specifically, an output O1 to a first output circuit and an output O2 to a second output circuit are connected at the output node N2.
The example of the related art latch circuit shown in FIG. 2 includes two input nodes N1 and N2, and two output nodes N3 and N4. In a manner similar to the latch circuit shown in FIG. 1, two input circuits (not shown) are connected to the latch circuit shown in FIG. 2. Specifically, an input I1 from a first input circuit is connected at the node N1, while an input I2 from a second input circuit is connected at the node N2. Moreover, in a manner similar to FIG. 1, two output circuits (not shown) are connected to the latch circuit. Specifically, an output O1 to a first output circuit is connected at the node N3, while an output O2 to a second output circuit is connected at the node N4.
The example of the related art latch circuit shown in FIG. 3 includes two input nodes N1 and N2, and two output nodes N3 and N4. Similar to the latch circuit shown in FIG. 1, the latch circuit shown in FIG. 3 is connected with two input circuits. Specifically, an input I1 and an input /I1 from a first input circuit are respectively connected to the node N1 and the node N2, while an input I2 from a second input circuit is connected at the node N1.
Moreover, similar to the latch circuit shown in FIG. 1, two output circuits (not shown) are connected to the latch circuit of FIG. 3. Specifically, an output O1 and an output /O1 to a first output circuit are respectively connected at the node N3 and the node N4, and an output O2 to the second output circuit is connected at the node N2.
The inputs I1 and /I1 and output O1 are used for the normal operation, and the input I2 and output O2 are used for a test operation. High-speed input and output are required for the inputs I1 and /I1 and the output O1, while the high-speed input and output are not required for the input I2 and output O2.
As shown in FIG. 1, the inputs I1 and I2 of the latch circuit, an input of a first inverter 1 and an output of a second inverter 2 are connected at the input node N1. The input I1 requires a high-speed input. However, because the other three circuit elements connected at the node N1 become a large load, the latch circuit cannot assure the high-speed input for the input I1.
As shown in FIG. 2, the input I1 of the latch circuit, the output of the first inverter 1, the input of the second inverter 2 and the input of the third inverter 3 are connected at the input node N1. The input I1 requires high-speed input. However, because the other three circuit elements connected at the node N1 become a large load, the latch circuit cannot assure the high-speed input for the input I1.
As shown in FIG. 3, the inputs I1 and I2 of the latch circuit, the output of the first inverter 1, the input of the second inverter 2 and the input of the third inverter 3 are connected at the input node N1. The input I1 requires high-speed input. However, because the other four circuit elements connected at the node N1 become a large load, the latch circuit cannot assure the high speed input for the input I1.
Moreover, as shown in FIG. 3, an input /I1, which is the complement signal of the first input I1 of the latch circuit, the output O2 of the latch circuit, the output of the second inverter 2, the input of the first inverter 1 and the input of the fourth inverter 4 are connected at the node N2. The input /I1 requires a high-speed input. However, because the other four circuit elements connected at the node N2 become a large load, the latch circuit cannot assure the high-speed input for the input /I1.